对比文件名称：2007-05-31_US2007124631A_发明申请_US20070124631A1 Bit field selection instruction
目标专利名称：482用于针对可变位宽度数据格式的打包和解包网络以及方法CN111788553B
模型名称：gpt-4o
## 特征比对表格
| 技术特征描述及公开性判断 | 对比文件原文引用 | 公开性论述 |
| **技术特征A**：《直接公开》 | **[0043]** "The processor includes an instruction cache and a data cache which are (typically via bus units, not shown) interfaced to an external memory/storage system. An instruction fetcher fetches instructions from the memory via the instruction cache."<br>**[0046]** "The permute instruction has three input source operands src1, src2, and src3 and an output destination operand dest."<br>**[0100]** "The instruction specifies a first source operand designator src1 and a second source operand designator src2, which in the example given, point at 128-bit registers R1 and R2, respectively." | 对比文件公开了处理器系统包含多个寄存器（如R1、R2、R3、R4等128位寄存器）作为数据存储位置，寄存器具有预定数目的位槽（128位）。这与目标专利中"第一多个位位置"的描述功能相同，都是用于临时存储位数据的寄存器结构。本领域技术人员能从对比文件直接得出与技术特征A相同的技术方案。 |
| **技术特征B**：《直接公开》 | **[0102]** "The value held in scr3 indicates which bit position in the source identified by src1 is to be copied into the least significant bit (LSB) of the result. The remaining bits of the result are taken from consecutive adjacent bits in the registers identified by src1 and src2, as shown." | 对比文件明确公开了位槽（bit position）用于存储和选择数据位，每个位槽可以存储相应的位数据。这与目标专利中"预定数目的位槽中的每个位槽均被配置为临时地存储预定数目的位的数据中的相应位"的功能完全相同。 |
| **技术特征C**：《直接公开》 | **[0005]** "In FIG. 1, the register holds sixteen bytes of eight bits each. In FIG. 2, the register holds eight words of sixteen bits each. In FIG. 3, the register holds four doublewords of thirty-two bits each. In FIG. 4, the register holds two quadwords of sixty-four bits each. In FIG. 5, the register holds one hundred twenty-eight single bits." | 对比文件公开了多种数据位宽度格式（8位、16位、32位、64位、1位等），对应目标专利中"若干不同数据位宽度"的概念，说明位槽的预定数目可以对应不同数据位宽度。 |
| **技术特征D**：《隐含公开》 | **[0078]** "FIG. 26 illustrates the functionality of a bit-wise bit field selection instruction. Its purpose is to shift a pair of source operands left by a number of bit positions specified by a control operand src3, and write the resulting shifted value to dest."<br>**[0079]** "The processor includes a 256-bit shifter (shown as 'sh')" | 对比文件公开了位字段选择指令用于移动数据位，但这是针对位移动的操作，不是专门的固定位打包网络。对比文件中的网络是用于执行旋转、移位等操作的通用位处理单元，不是一个"固定的"打包网络将多个位位置的位打包成位束。功能不同，不能直接公开技术特征D。 |
| **技术特征E**：《隐含公开》 | **[0102]** "The remaining bits of the result are taken from consecutive adjacent bits in the registers identified by src1 and src2"<br>**[0103]** "128 bits are selected from the R2:R1 conglomerate source" | 对比文件公开了从源寄存器的连续相邻位中选择位形成目标结果，但这是一种位选择操作，不是将多个位位置的相同位槽位置的位打包成位束的操作。功能不同。 |
| **技术特征F**：《隐含公开》 | **[0082]** "The processor then executes the byte-wise permute operation, writing the results to dest. Thus, the combination of a fine-grain (sub-byte) shift is used to get the operand data into a configuration in which a course-grain (byte-wise) permute can be used" | 对比文件公开了字节级排列操作中使用固定的临时寄存器（temp1、temp2等）进行数据传递，但这些是用于执行位字段选择指令的临时存储，不是用于位打包的"固定的点对点连接"。连接是动态生成的而非固定的。 |
| **技术特征G**：《直接公开》 | **[0005]** "In FIG. 1, the register holds sixteen bytes of eight bits each...In FIG. 3, the register holds four doublewords of thirty-two bits each."<br>**[0045]** "The present invention is centered on two capabilities: the ability to perform byte-wise permute operations, and the ability to perform bit-wise data manipulation operations" | 对比文件公开了处理器能够处理多种数据宽度（字节、字、双字等），即能"容纳输入到第一多个位位置的若干不同数据位宽度中的每一个"。 |
| **技术特征H**：《隐含公开》 | **[0078]** "Its purpose is to shift a pair of source operands left by a number of bit positions specified by a control operand src3, and write the resulting shifted value to dest." | 对比文件公开了数据从源操作数移动/打包到目的操作数，但这是位移动操作而非打包操作。功能有区别。 |
| **技术特征I**：《未公开》 | 无相关描述 | 对比文件未公开"第二多个位位置中使用的位位置比第一多个位位置少"的技术特征。对比文件中的操作不涉及将数据从多个源位置打包到更少的存储位置。 |
| **技术特征J**：《未公开》 | **[0043]** "The processor includes an instruction cache and a data cache which are (typically via bus units, not shown) interfaced to an external memory/storage system." | 对比文件提到存储器系统，但未公开"包含在存储器设备内的第二多个位位置，其中存储器设备还被配置为存储位束"。没有涉及位束存储在存储器中的概念。 |
| **技术特征K**：《未公开》 | 无相关描述 | 对比文件未公开"第二多个位位置包括存储器设备中的多个存储器单元"。 |
| **技术特征L**：《未公开》 | 无相关描述 | 对比文件未公开"位束中的位的数目对应于存储器设备的存储器数据字长"。没有涉及位束与存储器字长的对应关系。 |
| **技术特征M**：《隐含公开》 | **[0041]** "In one embodiment, the processor...include a dedicated byte permutation unit as one of the execution units."<br>**[0099]** "In one embodiment, the processor...include a dedicated bit manipulation unit." | 对比文件公开了字节排列单元和位操作单元作为执行单元的一部分，这些可以是计算数据路径网络或存储器数据路径中的一部分。 |
| **技术特征N**：《直接公开》 | **[0122]** "FIG. 45 illustrates the operation of a single instruction multiple data (SIMD) implementation of the bit field selection instruction. The instruction specifies a first SIMD source operation designator src1, a second SIMD source operand designator src2, and a SIMD destination designator dest, each of which points to, in the example shown, a respective 32-bit SIMD register which is treated as storing four 8-bit values or SIMD elements." | 对比文件明确公开了SIMD（单指令多数据）实现，公开了具有若干通道（4个8位SIMD元素）的SIMD单元，这与目标专利中"第一多个位位置中的位由具有若干通道的单指令多数据SIMD单元生成"完全相同。 |
| **技术特征O**：《隐含公开》 | **[0122]** "The 8-bit first SIMD element of src1 and the 8-bit first SIMD element of src2 are treated as a 16-bit value. The bit field instruction selects an 8-bit field from that 16-bit value and writes it into the first 8-bit SIMD element of dest." | 对比文件公开了SIMD处理，位字段选择操作对每个SIMD元素独立进行，位束大小（8位）与SIMD通道数（4个通道）存在倍数关系暗示。 |
| **技术特征P**：《未公开》 | **[0078]** "If the instruction specifies the same source as both src1 and src2, the bit field selection instruction has the effect of simply performing a rotation (rather than a shift) on src1." | 对比文件公开了旋转操作，但旋转是移位的一种形式（数据环绕），不是"解包操作"。对比文件未公开通过位打包网络的反向操作进行解包。 |
<<<A>>><<<B>>><<<C>>><<<G>>><<<M>>><<<N>>><<<a>>><<<b>>><<<c>>><<<d>>><<<e>>><<<f>>><<<h>>><<<o>>>