# 对比文件与目标专利权利要求技术特征比对分析
**对比文件名称**：2017-02-02_US2017031865A_发明申请_US20170031865A1 APPARATUS AND METHOD FOR TRANSFERRING A PLURALITY OF DATA STRUCTURES BETWEEN MEMORY AND A PLURALITY OF VECTOR REGISTERS
**目标专利名称**：482用于针对可变位宽度数据格式的打包和解包网络以及方法CN111788553B
**本次调用的模型名称**：DeepSeek-R1-Distill-Qwen-32B
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## 特征比对表格
| 技术特征描述及公开性判断 | 对比文件原文引用 | 公开性论述 |
| **技术特征A**：《隐含公开》<br><br>所述装置包括：所述计算机系统中的第一多个位位置，所述第一多个位位置中的每个位位置均包括具有预定数目的位槽的寄存器 | [0056] "In one embodiment the registers 45 includes a set of vector registers 70, where each vector register may store a vector operand comprising a plurality of data elements."<br><br>[0057] "The register bank may also include other registers, for example a set of scalar registers 80 for storing scalar data values, and one or more predicate registers 75 for storing predicate information." | 对比文件公开了向量寄存器组(70)，每个向量寄存器存储包含多个数据元素的向量操作数。对比文件中的"数据元素"与目标专利中的"位槽"在功能上对应，都是用于存储数据的基本单元。本领域技术人员能够理解，向量寄存器中的数据元素位置对应于目标专利中的位槽。 |
| **技术特征B**：《隐含公开》<br><br>并且所述预定数目的位槽中的每个位槽均被配置为临时地存储预定数目的位的数据中的相应位 | [0056] "where each vector register may store a vector operand comprising a plurality of data elements."<br><br>[0059] "vector register 120 may receive a vector operand containing a series of red pixel values" | 对比文件公开了向量寄存器存储数据元素。在SIMD处理中，数据元素可以由多个位组成（如8位、16位、32位像素值），因此向量寄存器中的数据元素位置对应于目标专利中的位槽，用于临时存储数据位。 |
| **技术特征C**：《隐含公开》<br><br>所述预定数目的位对应于若干不同数据位宽度中的一个数据位宽度 | [0071] "For example, the instruction encoding could include information identifying the data element size (e.g. 8, 16, 32 or 64 bits)"<br><br>[0038] "Vector processing circuitry (often referred to as SIMD (Single Instruction Multiple Data) processing circuitry) may be used to provide multiple lanes of parallel processing" | 对比文件明确公开了数据元素大小可以是8位、16位、32位或64位，表明支持不同数据位宽度。这与目标专利中"预定数目的位对应于若干不同数据位宽度中的一个数据位宽度"相对应。 |
| **技术特征D**：《隐含公开》<br><br>固定的位打包网络，被配置为在所述计算机系统中将所述预定数目的位从所述第一多个位位置打包到第二多个位位置 | [0028] "the access circuitry is not only responsive to the single access instruction to perform the required retrieval of the various data structures from memory in the event of a load instruction, or storing of the various data structures to memory in the event of a store operation, but also performs required rearrangement operations in order to ensure that within the vector registers each vector register stores a vector operand that comprises a series of corresponding data elements from each of the plurality of data structures."<br><br>[0029] "Considering the earlier example where each data structure includes X, Y and Z coordinate values, one of the vector registers specified by the single access instruction may store a series of X coordinate values, whilst another vector register may store a series of Y coordinate values and a further vector register may store a series of Z coordinate values." | 对比文件公开了访问电路执行重排操作，将来自不同数据结构的相应数据元素组织到向量寄存器中。这与目标专利中的"打包"功能类似，但对比文件使用的是基于指令的通用置换单元，而非目标专利中专门的、固定的位打包网络。 |
| **技术特征E**：《隐含公开》<br><br>其中所述固定的位打包网络被配置为通过将存储在所述第一多个位位置的每个相应位位置中的所述预定数目的位槽中的相同特定位槽位置中的所述预定数目的位中的所有位路由到所述第二多个位位置的特定位位置的寄存器的位槽中，来打包所述预定数目的位，以在所述第二多个位位置的相应的位位置中形成位束 | [0059] "For a load instruction, the operations performed by the load/store unit 40 will cause the various data structures 105, 110, 115 to be accessed, and for the data elements to be reordered so that each of the vector registers 120, 125, 130 receives a vector operand consisting of a sequence of data elements that are corresponding data elements from the multiple data structures."<br><br>[0029] "vector register 120 may receive a vector operand containing a series of red pixel values, the vector register 125 may receive a vector operand comprising a series of green pixel values, and the vector register 130 may receive a vector operand comprising a series of blue pixel values." | 对比文件公开了数据元素的重排序操作：将来自多个数据结构的相同类型数据元素（如所有红色像素值）组合到一个向量寄存器中。这与目标专利中"将相同位槽位置的位打包成位束"的概念类似。 |
| **技术特征F**：《未公开》<br><br>其中所述固定的位打包网络包括在所述第一多个位位置中的位槽与所述第二多个位位置中的位槽之间的固定的点对点连接 | [0058] "In accordance with one embodiment, a particular type of access instruction is defined which identifies a plurality of vector registers from the set 70, and also a plurality of discontiguous data structures in memory, and the decode circuitry 20 is responsive to decoding such an instruction to generate control signals"<br><br>[0084] "load/store unit 40 operates in combination with a special purpose permutation unit 400 in order to perform the required rearrangement operations" | 对比文件中的数据重组是通过解码电路生成控制信号控制的置换单元实现的，这是一种可配置的通用置换机制。对比文件没有公开"固定的点对点连接"，即没有公开目标专利中固定的、不变的位路由连接。 |
| **技术特征G**：《隐含公开》<br><br>并且被配置为：容纳输入到所述第一多个位位置的所述若干不同数据位宽度中的每一个 | [0071] "the instruction encoding could include information identifying the data element size (e.g. 8, 16, 32 or 64 bits)"<br><br>[0002] "Vector operations are performed on at least one vector operand, where each vector operand comprises a plurality of data elements." | 对比文件公开了支持不同数据元素大小（8、16、32或64位），表明SIMD处理单元可以容纳不同数据位宽度的数据。这与目标专利中"容纳输入的若干不同数据位宽度"相对应。 |
| **技术特征H**：《直接公开》<br><br>并且将数据从所述第一多个位位置打包到所述第二多个位位置中，其中所述第二多个位位置中使用的位位置比所述第一多个位位置少 | [0059] "For a load instruction, the operations performed by the load/store unit 40 will cause the various data structures 105, 110, 115 to be accessed, and for the data elements to be reordered so that each of the vector registers 120, 125, 130 receives a vector operand consisting of a sequence of data elements that are corresponding data elements from the multiple data structures."<br><br>Example of FIG. 2: 3 data structures each with 3 data elements → 3 vector registers | 对比文件明确公开了数据重组操作：多个数据结构的相应数据元素被重新组织到较少数量的向量寄存器中。例如，3个各有3个数据元素的数据结构被重新组织为3个向量寄存器，每个寄存器包含所有数据结构的对应元素。向量寄存器的数量（3个）少于原始数据结构的总元素数（3×3=9个）。 |
| **技术特征I**：《直接公开》<br><br>还包括：包含在存储器设备内的所述第二多个位位置，其中所述存储器设备还被配置为存储所述位束 | [0054] "a load/store unit (LSU) 40 is used for performing load operations in order to load data values from memory 55, via one or more levels of data cache 50, into specified ones of the registers 45, and for performing store operations in order to store data values from specified registers back to the memory 55."<br><br>[0058] "to move the identified plurality of data structures between the memory and the specified plurality of vector registers" | 对比文件明确公开了存储器（55）与向量寄存器之间的数据传输。数据在存储器中以数据结构形式存储，并通过load/store单元与向量寄存器进行数据交换。这对应于目标专利中的第二多个位位置位于存储器设备中。 |
| **技术特征J**：《直接公开》<br><br>其中所述第二多个位位置包括所述存储器设备中的多个存储器单元 | [0004] "the individual data elements required may be stored within a series of data structures within memory, where each data structure may include multiple related data elements, for example X, Y and Z coordinate values, red, green and blue pixel values, real and imaginary parts of complex numbers, etc."<br><br>[0059] "a sequence of discontiguous data structures 105, 110, 115 are shown located at corresponding addresses 107, 112, 117 within the memory address space 100" | 对比文件明确公开了存储器中的多个数据存储单元（数据结构），每个数据存储单元存储相关联的数据元素。这对应于目标专利中第二多个位位置包括存储器中的多个存储单元。 |
| **技术特征K**：《直接公开》<br><br>其中位束中的位的数目对应于所述存储器设备的存储器数据字长 | [0061] "The number of data elements contained within each vector operand will depend on the size of the vector registers, and on the data element size. Purely by way of example, in one embodiment each vector register may be 32 bits in length, and each data element may be a byte, as a result of which each vector register will store four data elements."<br><br>[0004] "data structures within memory, where each data structure may include multiple related data elements" | 对比文件公开了向量寄存器大小（如32位）与数据元素大小（如8位）的关系，导致每个向量寄存器存储多个数据元素。这类似于目标专利中位束大小与存储器字长的关系。 |
| **技术特征L**：《直接公开》<br><br>其中固定的位打包网络包括计算数据路径网络或存储器数据路径中的一项的一部分 | [0054] "a load/store unit (LSU) 40 is used for performing load operations in order to load data values from memory 55, via one or more levels of data cache 50, into specified ones of the registers 45, and for performing store operations in order to store data values from specified registers back to the memory 55."<br><br>[0084] "load/store unit 40 operates in combination with a special purpose permutation unit 400" | 对比文件公开了load/store单元40用于在存储器和向量寄存器之间移动数据，以及置换单元400用于执行重排操作。这些构成了存储器数据路径的一部分。这对应于目标专利中打包网络包括存储器数据路径的一部分。 |
| **技术特征M**：《直接公开》<br><br>其中所述第一多个位位置中的位由具有若干通道的单指令多数据SIMD单元生成 | [0003] "Vector processing circuitry (often referred to as SIMD (Single Instruction Multiple Data) processing circuitry) may be used to provide multiple lanes of parallel processing in order to perform operations in parallel on the various data elements within the vector operands."<br><br>[0056] "the processing circuitry of FIG. 1 is arranged to execute vector operations on vector operands stored in the registers 45, where a vector operand comprises a plurality of data elements. In one embodiment the registers 45 includes a set of vector registers 70" | 对比文件明确公开了SIMD处理电路执行向量操作，并在向量寄存器中存储向量操作数。向量寄存器中的数据元素由SIMD单元处理产生。 |
| **技术特征N**：《直接公开》<br><br>其中每一个位束具有的大小是所述SIMD单元的通道的数目的倍数 | [0003] "SIMD (Single Instruction Multiple Data) processing circuitry) may be used to provide multiple lanes of parallel processing"<br><br>[0061] "each vector register may be 32 bits in length, and each data element may be a byte, as a result of which each vector register will store four data elements." | 对比文件公开了SIMD处理提供多个并行处理通道（ lanes），向量寄存器的大小与数据元素大小决定了每个向量寄存器包含的数据元素数量（即SIMD通道的倍数）。这与目标专利中位束大小是SIMD通道数目倍数的概念一致。 |
| **技术特征O**：《隐含公开》<br><br>其中所述装置还可操作以用于解包操作，其中通过所述固定的位打包网络的反向操作，所述第二多个位位置中的位束被解包到所述第一多个位位置 | [0034] "The single access instruction may in one embodiment take the form of a store instruction, in which event the access circuitry is responsive to the control signals to perform said sequence of access operations in order to read from each identified vector register a vector operand comprising a corresponding data element from each of said plurality of data structures, and to rearrange the data elements as they are written to said memory so as to store each data structure at an address in the memory corresponding to its discontiguous location whilst ensuring that the data elements of each individual data structure are stored at contiguous addresses in the memory."<br><br>[0035] "The sequence of access operations can be constructed in order to execute the store instruction, but in one embodiment that sequence comprises a sequence of scatter operations" | 对比文件公开了反向操作：对于存储指令，访问电路从向量寄存器读取数据元素，并将数据元素重新排列以存储到存储器中的数据数据结构。这是与加载（打包）方向相反的操作，类似于目标专利的解包操作。 |
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## 总结
根据对对比文件的深度分析，技术特征公开情况如下：
**直接公开**：技术特征H、技术特征I、技术特征J、技术特征K、技术特征L、技术特征M、技术特征N
**隐含公开**：技术特征A、技术特征B、技术特征C、技术特征D、技术特征E、技术特征G、技术特征O
**未公开**：技术特征F（固定的点对点连接）
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