## 对比文件名称
2008-10-23_WO2008126041A_发明申请_WO2008126041A1 METHOD OF STORING DATA, METHOD OF LOADING DATA AND SIGNAL PROCESSOR
## 目标专利名称
482用于针对可变位宽度数据格式的打包和解包网络以及方法CN111788553B
## 模型名称
Claude (Claude 4 Sonnet)
---
## 特征比对表格
| 技术特征 | 对比文件引用 | 公开性论述 |
| **技术特征A**：《直接公开》 | **[p0033]**: "The register file has a set of registers R1, R2, R3. Each register is capable of storing a vector with data elements in respective register elements R11, ..., R18."<br><br>**[p0034]**: "The vector elements have a size of n bits e.g. 10 or 12 that is smaller than the size, e.g. 16 bits, of the register elements."<br><br>**[p0040]**: "the process data elements having a size of n=10 bits, are temporarily present in respective register elements R11, ..., R18 of a register R1 of a register file RF. The size of the register elements is 16 bits." | 对比文件在[p0033]中明确公开了"寄存器文件RF具有一组寄存器R1、R2、R3。每个寄存器能够以相应的寄存器元素R11,...,R18存储具有数据元素的向量"。在[p0034]中公开了"向量元素具有n位的大小（例如10或12位），小于寄存器元素的大小（例如16位）"。在[p0040]中进一步确认了这一点。对比文件中的寄存器元素R11-R18对应于目标专利中的"第一多个位位置"，每个寄存器元素对应于目标专利中的"具有预定数目的位槽的寄存器"。由于寄存器元素的大小为16位，这表明每个寄存器元素具有预定数目的位槽（16个位槽）。因此，技术特征A被直接公开。 |
| **技术特征B**：《直接公开》 | **[p0040]**: "the process data elements having a size of n=10 bits, are temporarily present in respective register elements R11, ..., R18 of a register R1 of a register file RF. The size of the register elements is 16 bits."<br><br>**[p0044]**: "In the second step S2 bits are exchanged between mutually subsequent process data elements D1-D8 in the vector in an amount and a direction dependent on the comparison and on the location of the process data elements within the vector. Exchanging bits in step S2 results in a vector of modified data elements Dm1-Dm8." | 对比文件在[p0040]中明确公开了过程数据元素（例如10位大小）临时存储在相应的寄存器元素R11,...,R18中。寄存器元素的大小为16位，因此能够存储预定数目的位（10位数据）。在[p0044]中公开了位交换操作导致修改的数据元素。这对应于目标专利中"预定数目的位槽中的每个位槽均被配置为临时地存储预定数目的位的数据中的相应位"。因此，技术特征B被直接公开。 |
| **技术特征C**：《直接公开》 | **[p0034]**: "The vector elements have a size of n bits e.g. 10 or 12 that is smaller than the size, e.g. 16 bits, of the register elements."<br><br>**[p0040]**: "the process data elements having a size of n=10 bits, are temporarily present in respective register elements R11, ..., R18 of a register R1 of a register file RF." | 对比文件在[p0034]中明确公开了"向量元素具有n位的大小，例如10或12位"，即存在不同的数据位宽度（10位或12位）。在[p0040]中进一步公开了过程数据元素具有n=10位的大小。这对应于目标专利中"预定数目的位对应于若干不同数据位宽度中的一个数据位宽度"。因此，技术特征C被直接公开。 |
| **技术特征D**：《直接公开》 | **[p0017]**: "According to the invention a method is provided for storing a vector of data elements that have a size of n bits from a register file into a memory, the memory being arranged for storage of a vector of storage data elements in locations having a size of m bits, wherein m>n, the method comprising the steps of: exchanging bits between process data elements in the vector stored in mutually subsequent register file elements, the step of exchanging resulting in a vector of modified data elements, shuffling groups of k subsequent bits in the resulting vector, storing the resulting shuffled vector of modified data elements as a vector of storage data elements in the memory."<br><br>**[p0024]**: "According to the object of the present invention a digital signal processor comprises: one or more functional units, a register file comprising a first plurality of register elements for storing at least a vector of process data elements that have a size of n bits, a memory for storing at least one vector in a plurality of memory locations having a size of m bits, wherein m>n, a shuffle unit for shuffling data elements having a size of k bits of a vector, characterized by an exchange facility for exchanging bits between mutually subsequent data elements of a vector." | 对比文件在[p0017]中公开了"一种用于将具有n位大小的数据元素的向量从寄存器文件存储到存储器中的方法"，该方法包括交换位和混洗操作。在[p0024]中公开了数字信号处理器包括"寄存器文件，包括用于存储至少一个具有n位大小的过程数据元素的向量的第一多个寄存器元素"和"用于对向量中具有k位大小的数据元素进行混洗的混洗单元"。这对应于目标专利中的"固定的位打包网络，被配置为在所述计算机系统中将所述预定数目的位从所述第一多个位位置打包到第二多个位位置"。因此，技术特征D被直接公开。 |
| **技术特征E**：《直接公开》 | **[p0019]**: "Shuffle operations are already supported in some SIMD processors. A shuffle has two source vectors s and r, and one target vector t. With index i, 0 ≤ i < P, this operation can be specified by t[i] = s[r[i]] for all i. In words, element i of target vector t is copy of the element from s specified by index r[i]."<br><br>**[p0044]**: "In the second step S2 bits are exchanged between mutually subsequent process data elements D1-D8 in the vector in an amount and a direction dependent on the comparison and on the location of the process data elements within the vector. Exchanging bits in step S2 results in a vector of modified data elements Dm1-Dm8."<br><br>**[p0051]**: "In step S3 groups of k subsequent bits (here k = 8) in the resulting vector Dm1-Dm8 are shuffled. Accordingly, each of the registers elements R11-R15 used for storing the modified data elements comprises 16 bits of data, and is fully occupied therewith." | 对比文件在[p0019]中公开了混洗操作的具体实现方式。在[p0044]中公开了位交换操作。在[p0051]中公开了"在步骤S3中，结果向量Dm1-Dm8中的k个连续位组（此处k=8）被混洗"。这对应于目标专利中"通过将存储在所述第一多个位位置的每个相应位位置中的所述预定数目的位槽中的相同特定位槽位置中的所述预定数目的位中的所有位路由到所述第二多个位位置的特定位位置的寄存器的位槽中，来打包所述预定数目的位，以在所述第二多个位位置的相应的位位置中形成位束"。虽然术语不完全相同，但本质上传达了相同的技术含义，即将数据元素中相同位置的数据分组并路由到目标位置以形成位束。因此，技术特征E被直接公开。 |
| **技术特征F**：《隐含公开》 | **[p0019]**: "Shuffle operations are already supported in some SIMD processors. A shuffle has two source vectors s and r, and one target vector t. With index i, 0 ≤ i < P, this operation can be specified by t[i] = s[r[i]] for all i."<br><br>**[p0035]**: "The register files are coupled with a first data path DP1, having parallel data lanes DP11, ...,DP18 to an exchange facility EF, comprising a plurality of exchange units EF1,...,EF8. Each exchange unit EFj is capable of exchanging data bits with its neighboring exchange unit(s). The exchange units EFj are coupled to a shuffle unit SF via a second data path DP2 having parallel data lanes DP21,...,DP28." | 对比文件在[p0035]中公开了寄存器文件通过第一数据路径DP1耦合到交换设施EF，交换单元EFj通过第二数据路径DP2耦合到混洗单元SF。虽然没有明确使用"固定的点对点连接"这一术语，但[p0019]中公开的混洗操作是预先定义的映射关系（t[i] = s[r[i]]），这暗示了固定的数据路由连接。本领域技术人员可以理解，这种固定的映射关系需要通过固定的点对点连接来实现。因此，技术特征F被隐含公开。 |
| **技术特征G**：《直接公开》 | **[p0037]**: "The exchange facility EF may be arranged for exchanging data elements between subsequent register elements according to a predetermined pattern. For example, for compressing process data elements having a size of 10 bits, Such an exchange facility is suitable if process data of a single type has to be compressed. In a preferred embodiment however, the exchange facility is controllable. In this way multiple values of m can be supported."<br><br>**[p0040]**: "the process data elements having a size of n=10 bits, are temporarily present in respective register elements R11, ..., R18 of a register R1 of a register file RF. The size of the register elements is 16 bits." | 对比文件在[p0037]中明确公开了"交换设施EF可以布置为根据预定模式在后续寄存器元素之间交换数据元素"以及"在优选实施例中，交换设施是可控制的。通过这种方式，可以支持多个m值"。这表明交换设施能够容纳不同的数据位宽度。目标专利中的技术特征G要求"被配置为：容纳输入到所述第一多个位位置的所述若干不同数据位宽度中的每一个"。对比文件在[p0037]中明确公开了这一点，因此技术特征G被直接公开。 |
| **技术特征H**：《直接公开》 | **[p0017]**: "According to the invention a method is provided for storing a vector of data elements that have a size of n bits from a register file into a memory, the memory being arranged for storage of a vector of storage data elements in locations having a size of m bits, wherein m>n, the method comprising the steps of: exchanging bits between process data elements in the vector stored in mutually subsequent register file elements, the step of exchanging resulting in a vector of modified data elements, shuffling groups of k subsequent bits in the resulting vector, storing the resulting shuffled vector of modified data elements as a vector of storage data elements in the memory." | 对比文件在[p0017]中明确公开了"一种用于将具有n位大小的数据元素的向量从寄存器文件存储到存储器中的方法"，该方法包括交换位、混洗和存储步骤。这对应于目标专利中的"将数据从所述第一多个位位置打包到所述第二多个位位置中"。因此，技术特征H被直接公开。 |
| **技术特征I**：《直接公开》 | **[p0040]**: "the process data elements having a size of n=10 bits, are temporarily present in respective register elements R11, ..., R18 of a register R1 of a register file RF. The size of the register elements is 16 bits."<br><br>**[p0041]**: "The memory M is arranged for storage of storage data elements of vectors in locations M1,....,M5. The locations M1,...,M5 of the memory have a size m greater than the size n of the first data elements D1,...,D8. In this case m =16 bits." | 对比文件在[p0040]中公开了过程数据元素（10位大小）临时存储在8个寄存器元素R11,...,R18中。在[p0041]中公开了存储器位置M1,...,M5用于存储数据元素。由于10位数据元素被打包后只需要5个存储位置（而不是8个），这表明第二多个位位置中使用的位位置比第一多个位位置少。这对应于目标专利中的技术特征I。因此，技术特征I被直接公开。 |
| **技术特征J**：《直接公开》 | **[p0041]**: "The memory M is arranged for storage of storage data elements of vectors in locations M1,....,M5. The locations M1,...,M5 of the memory have a size m greater than the size n of the first data elements D1,...,D8. In this case m =16 bits."<br><br>**[p0054]**: "Then, in step S4 the resulting shuffled vector Vs of modified data elements is stored as a vector of second data elements in the memory M." | 对比文件在[p0041]中明确公开了"存储器M被布置为在位置M1,...,M5中存储向量的存储数据元素"。在[p0054]中公开了"在步骤S4中，结果混洗向量Vs的修改数据元素作为第二数据元素的向量存储在存储器M中"。这对应于目标专利中的"还包括：包含在存储器设备内的所述第二多个位位置，其中所述存储器设备还被配置为存储所述位束"。因此，技术特征J被直接公开。 |
| **技术特征K**：《直接公开》 | **[p0041]**: "The memory M is arranged for storage of storage data elements of vectors in locations M1,....,M5. The locations M1,...,M5 of the memory have a size m greater than the size n of the first data elements D1,...,D8. In this case m =16 bits." | 对比文件在[p0041]中明确公开了"存储器M被布置为在位置M1,...,M5中存储向量的存储数据元素"。这些存储位置M1,...,M5对应于目标专利中的"存储器设备中的多个存储器单元"。因此，技术特征K被直接公开。 |
| **技术特征L**：《直接公开》 | **[p0041]**: "The memory M is arranged for storage of storage data elements of vectors in locations M1,....,M5. The locations M1,...,M5 of the memory have a size m greater than the size n of the first data elements D1,...,D8. In this case m =16 bits."<br><br>**[p0051]**: "In step S3 groups of k subsequent bits (here k = 8) in the resulting vector Dm1-Dm8 are shuffled. Accordingly, each of the registers elements R11-R15 used for storing the modified data elements comprises 16 bits of data, and is fully occupied therewith." | 对比文件在[p0041]中公开了存储位置的大小为m=16位。在[p0051]中公开了每个寄存器元素包含16位数据并被完全占用。混洗后的数据被打包成16位的存储数据元素存储在存储器中。这对应于目标专利中的"其中位束中的位的数目对应于所述存储器设备的存储器数据字长"。因此，技术特征L被直接公开。 |
| **技术特征M**：《隐含公开》 | **[p0033]**: "Fig. 2 schematically shows a vector processor according to the present invention. The vector processor comprises a plurality of functional units FU1, ...,FUn, that are coupled to a register file RF."<br><br>**[p0038]**: "On its turn, the shuffle unit SF is coupled via a data path DP3, with data lanes DP31, ..., DP38 to a memory M. Each data lane DP31, ..., DP38 is coupled to a respective memory bank. The memory M is capable of storing at least one vector in a plurality of memory locations having a size of m bits, wherein m>n. For example m = 16." | 对比文件在[p0033]中公开了向量处理器包括多个功能单元FU1,...,FUn耦合到寄存器文件RF。在[p0038]中公开了混洗单元SF通过数据路径DP3耦合到存储器M。这暗示了数据路径网络的存在。目标专利中的技术特征M要求"其中固定的位打包网络包括计算数据路径网络或存储器数据路径中的一项的一部分"。对比文件中的数据路径DP1、DP2、DP3可以理解为计算数据路径或存储器数据路径的一部分。因此，技术特征M被隐含公开。 |
| **技术特征N**：《直接公开》 | **[p0005]**: "Signal processing e.g. for audio and video processing usually requires that the same instruction is repeated for a plurality of data elements of a vector. An example of such a processor, here an SIMD processor, is shown in Fig. 1."<br><br>**[p0033]**: "Fig. 2 schematically shows a vector processor according to the present invention. The vector processor comprises a plurality of functional units FUl, ...,FUn, that are coupled to a register file RF." | 对比文件在[p0005]中明确公开了"SIMD处理器"用于信号处理，并且同一指令被重复用于向量的多个数据元素。在[p0033]中进一步公开了向量处理器包括多个功能单元耦合到寄存器文件RF。这对应于目标专利中的"其中所述第一多个位位置中的位由具有若干通道的单指令多数据SIMD单元生成"。因此，技术特征N被直接公开。 |
| **技术特征O**：《隐含公开》 | **[p0007]**: "The memory M has a storage capacity for a plurality of vectors, each comprising P words of m bits. For example P = 8 and m = 16. The functional units FUs support multiple operations in parallel on data stored in the register file, such as load and storage of data, multiplication, and multiply accumulate operations."<br><br>**[p0041]**: "The memory M is arranged for storage of storage data elements of vectors in locations M1,....,M5. The locations M1,...,M5 of the memory have a size m greater than the size n of the first data elements D1,...,D8. In this case m =16 bits." | 对比文件在[p0007]中公开了存储器M的存储容量用于多个向量，每个向量包括P个字，每个字m位，例如P=8，m=16。在[p0041]中公开了5个存储位置M1,...,M5用于存储向量数据元素。由于P=8个数据元素被打包成5个存储位置，位束的大小（存储效率）与SIMD单元的通道数P=8相关。本领域技术人员可以理解，存储的数据量是SIMD通道数的函数。因此，技术特征O被隐含公开。 |
| **技术特征P**：《直接公开》 | **[p0023]**: "Analogously a method according to the invention is provided for loading a vector of storage data elements that are stored in memory locations that have a size of m bits of a memory as a vector of process data elements that have a size of n bits into a register file, wherein m>n, the method comprising the steps of: retrieving a vector of storage data elements from the memory, applying a shuffling wherein two or more groups of k subsequent bits are exchanged in their entirety resulting in a shuffled vector, exchanging bits between pairs of data elements in the shuffled vector stored in subsequent register elements, the exchanging resulting in a vector of modified data elements."<br><br>**[p0056]-[p0066]**: 详细描述了加载方法的步骤，包括检索、混洗和位交换操作。 | 对比文件在[p0023]中明确公开了"类似地，本发明提供了一种用于将存储数据元素的向量从存储器加载为过程数据元素的向量到寄存器文件中的方法"，该方法包括检索、混洗和位交换步骤。这对应于目标专利中的"其中所述装置还可操作以用于解包操作，其中通过所述固定的位打包网络的反向操作，所述第二多个位位置中的位束被解包到所述第一多个位位置"。存储过程和加载过程是相反的操作，存储是打包，加载是解包。因此，技术特征P被直接公开。 |
---
## 技术特征公开性判断汇总
| 技术特征 | 公开性判断 |
| A | 直接公开 |
| B | 直接公开 |
| C | 直接公开 |
| D | 直接公开 |
| E | 直接公开 |
| F | 隐含公开 |
| G | 直接公开 |
| H | 直接公开 |
| I | 直接公开 |
| J | 直接公开 |
| K | 直接公开 |
| L | 直接公开 |
| M | 隐含公开 |
| N | 直接公开 |
| O | 隐含公开 |
| P | 直接公开 |
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